The HyperTransport communications bus got a boost on Monday, with the release of a new, speedier specification and an update to its external connector.
HyperTransport 3.1 will give aggregate transfer performance of 51.6GB per second (or 6.4 gigatransfers per second), according to the HyperTransport Consortium, which published the new specification. The update should give a lift to the technology, which was introduced seven years ago.
Version 2 of the interconnect technology is used in AMD's dual-core processors, and version 3, introduced in 2006, is in its quad-core chips. HyperTransport technology is also used by Broadcom, Nvidia, Sun and Cisco, in other applications. Version 3.1 increases the maximum clock rate of the bus, from 2.6GHz up to 3.2GHz.
The new specification will take six months to a year to filter out into delivered products, said Mario Cavalli, general manager of the HyperTransport Consortium, which has managed the HyperTransport specification since AMD handed it over in 2001. "We provide an opportunity, and there is always a time gap between when we announce the specification and when products arrive," Cavalli told ZDNet.co.uk.
The new version of HyperTransport has been compared to the external PCI Express bus, which is due to move to version 3.0 next year, going from 16GB per second to 32GB per second.
Although HyperTransport does have its associated HTX external slot connector, the buses are fundamentally different, Cavalli said. "HyperTransport is in a category of its own; it is a technology that offers tremendously low latency," said Cavalli. Latency is the time taken to finish a transaction.
"In a nutshell, PCI Express is an interconnect for peripheral devices, while HTX is for co-processing technology. Processors always have to communicate in fast mode, with low latency," he added.
The HTX external slot connector got its own version 3.0 update, to HTX3, on Monday. It now promises up to 5.2 gigatransfers per second bandwidth (2.6GHz clock rate), according to the HyperTransport Consortium.
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Earlier versions of HTX had 55 percent lower latency than the comparable PCI Express bus, according to figures from the consortium.
HyperTransport will be in more than 60 million devices by the end of 2008, according to figures from In-Stat quoted by Cavalli, who acknowledged that, so far, the vast majority of these systems are AMD processors using the bus internally. However, the bus is even used in Intel-based systems, for instance, in Nvidia devices that use HyperTransport between the north bridge and south bridge.
AMD will not discuss delivery dates for HyperTransport 3.1, but it has delivered version 3 in desktop products and is due to ship server products including HyperTransport 3 in the first half of 2009, according to Jon Carvill, head of public relations for AMD EMEA.
The HyperTransport concept has won converts elsewhere, he claimed: "Intel has moved to a new architecture for multicore which is effectively an Intel variant of HyperTransport," said Cavalli. "That's a validation of what we are doing. They have adopted all the things we did three or four years ago."
