...the silicon atoms to either stretch or compress the bonds between them, which improves their conductivity and thus the speed at which the transistor can operate.
By varying the size of the gate and the voltages with which the transistor operates, it is possible to configure it to run very fast but with some inefficiency — more electricity leaks, thus increasing power consumption — or slower but with much less leakage. So far, this technique has been one of the key differentiators between Intel's high power chips such as the Pentium 4 and its portable devices typified by the Pentium M. However, the variation possible by such methods is limited
Thus Intel has created a modified version of the 65nm process, called P1265, which creates transistors with dramatically lower leakage. There are three ways that electricity can leak through a transistor when it's turned off — across the transistor, from the gate into the transistor, or from parts of the transistor into the silicon on which it's mounted. The first leakage path can be reduced by increasing the voltage at which the transistor starts to operate, the second by increasing the thickness of the insulating layer and the third by what Intel calls 'low damage' engineering. Bohr wouldn't elaborate on that, except to say that it involves creating that part of the transistor with increased precision.
These techniques can reduce the leakage current per transistor to around 0.3pA, or a third of a billionth of an amp. That's around 1,000 times better than the unmodified 65nm transistors, and should result in processors that run at less than 1W under some conditions — although Intel is a long way from announcing any hard figures, or even which products may use the new transistor technology.
Intel has built experimental 50Mb static memory chips with the new process, created around the company's standard six transistor per cell design. These chips have more than 350 million transistors, and test every technique used in creating processors. While Intel is not revealing any figures, Bohr said that the chip was a challenging test vehicle that was behaving well and demonstrating ultra-low leakage. "We're ahead of all our competitors," he said, "in how well our transistors work while having such low leakage".
While there is plenty of legitimate discussion about the long term physical viability of Moore's Law and its role as a primary driver in the dynamics of the chip industry, it is clear from meeting people like Bohr that the engineers at the cutting edge of making the chips work are confident that their promises will be fulfilled.
