Chip packaging is arcane, often overlooked and absolutely crucial to the future of the semiconductor industry. Intel on Monday is unveiling an entirely new design for the silicon and metal vehicles that connect the microprocessor to the rest of the computer. The company says the breakthrough will play an essential role in allowing processing power to grow. Five years from now, microprocessors will run at 20GHz; they'll need to issue and receive a vast amount of signals and will require a high infusion of electricity. Bumpless Build-Up Layer (BBUL) packaging will essentially channel all that traffic through an extremely thin web of interconnections--tiny wires that link chip circuits--surrounding the chip. BBUL, set to go to work in five to six years, allows a far more ornate web than can be produced through current packaging technology. "Your package interconnect density has to be extremely complex," said Koushik Banerjee, the technical adviser for the Assembly Technology Development department at Intel. "The part that is going to kill performance in the future is the interconnect length." How the chip fits into the package will also change. Currently, chips sit on top of the package. With BBUL, the chip will be embedded entirely in the package because the package will be grown around the chip through the same lithographic principles used to build the chips in the first place. Packaging has never been one of the glamorous jobs in the chip industry. "It's been the ignored child in the semiconductor family," said Nathan Brookwood, an analyst at Insight 64. The main function performed by a package is to create electrical connections between the chip and the motherboard. The increasing complexity of processors combined with the decreasing size of the chip, however, have pushed packaging to the forefront. Some chips feature 5,000 or more surface ports that must be electrically connected to the inside surface of the package, according to Banerjee. Similarly, the number of package-to-motherboard connections, called pins, has ballooned to close to 500 on many chips. Processor power requirements also continue to climb, as do noise, heat and the possibility of signal interference. "It doesn't do you a lot of good if you do all these calculations on a chip and can't get it out," said Linley Gwennap, principal analyst at The Linley Group. "The more power you have, the more pins you need to take power in and out of the chip...It's a real problem." Problems are likely to only get worse. Package manufacturers will have to contend with managing even more signals traveling at a faster rate across more circuits squeezed into a denser piece of silicon, which will need more electricity than a high-powered lightbulb. And any solution will have to be cheap. "We can deliver a lot of cool technology in the lab, (but) it's really irrelevant unless you can scale it to millions of units at a low cost," he said. As a result, packaging research ranks up with the company's work on Extreme Ultraviolet (EUV) lithography, copper interconnects and transistor speed, Banerjee said. A total of 900 engineers at four different sites are working on package issues, he added. BBUL differs from current packaging in its stuffed-pizza approach. Currently, chips are glued onto a package that resembles a small circuit board. The electrical connections between the two parts are accomplished through a series of solder "bumps". The package then connects to the motherboard through a series of pins--the metallic posts you can see on the back of a processor. With BBUL, Intel will dig a trench into the packaging material, insert the microprocessor core, and then encase it in layers of copper and silicon, which perform the same function as the bumps. These layers will be applied through the similar, although less advanced, lithography and etching techniques used to produce the main chip. "This gives Intel a chance to use lithography tools that are much coarser than you can use with microprocessors," which let the chipmaker recycle old equipment, Brookwood said. The advantages are numerous. The copper and silicon layers provide more, and more minute, electrical connections than are possible with solder bumps. The silicon layers are thinner as well, reducing the length of the interconnects and improving overall performance. Multi-chip modules could also be constructed with BBUL, said Banerjee. A battery of chips could be inserted into one package to reduce real estate inside handheld computers and other space-constrained gadgets. Two server processors could also be coupled in a package. Such a server chip wouldn't replicate the performance of a two-core chip (such as IBM's Power 4), but it would deliver more punch than current two-processor configurations, he said. BBUL packages will also be useful for more evenly distributing power supplies. Currently, most chips receive power from a large, centralised capacitor. In the future, Intel will distribute smaller capacitors throughout parts of the chip. More direct connections mean quicker power transfer and better signal integrity. Eventually, these techniques could be used to improve the package to motherboard connectors. "Pins are not at all that great for bringing in power, especially when you are trying to get pins into a smaller and smaller area," Brookwood said. "The big issue the packaging guys are having is the pin count," Gwennap added. See Chips Central for the latest headlines on processors and semiconductors. See the Hardware News Section for full coverage. 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