As semiconductor technology marches forward, following Moore's Law, chips get smaller and faster, but they also pack more transistors. Doubling the number of transistors yet fitting them into tighter confines, which happens with every manufacturing process generation, exacerbates certain problems, such as current leakage and interference between transistors. Ultimately, "power consumption will probably become the limiter...because as we put more and more transistors per unit area, if we don't keep the power density flat, we can't use the chip," said Bijan Davari, vice president of semiconductor development at IBM Microelectronics. Sure, chips could still be manufactured, Davari said, but they would be use too much power to be practical for use in home PCs or cellular phones. To hold power down, "you need to fundamentally change some of the things the industry has been using for 30 years to keep the performance increase going," Davari said. Fortunately, "the way to do it is exactly the same solution that we use for high performance." That means developing new materials, such as silicon on insulator, that hold down power consumption or make chips run faster by making transistors more efficient. But just because reducing power is possible, doesn't mean it's easy, said Fred Zieber, president of research firm Pathfinder Research. Power "is going to be a hot topic as far as you can see," Zieber said. "As you get to higher and higher densities and more and more transistors and gates on a chip, power is becoming really important. It's something that's across the board, not just portables." The voltage island concept, "is a very nice addition to IBM's (90 nanometre) process and something I think you'll see increasingly as people go to that dimension," Zieber said. "As you move to (90 nanometres) and below, there's a lot of stuff that the industry hasn't had to address before. That's why these guys are working on it" at the conference.
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