The convention will also mark the latest episode in the ongoing research and development battle between IBM and Intel. The two companies are largely the leaders in the field, but certainly not friends. IBM often points out that it is responsible for many semiconductor design breakthroughs, such as using copper rather than aluminum wire to connect circuits. Intel counters that it sells far more chips than IBM does. As previously reported, IBM researchers are slated to present three papers on their efforts to build a double-gate transistor using the Fin Field Effect Transistor (Fin-Fet) approach. These transistors could be used to control power consumption, among other things, in future chips. IBM Microelectronics also plans to unveil a paper on its new 350GHz communications transistor, announced last week. Meanwhile, IBM Research has lined up a paper on 3D circuit designs, which use two or more layers of transistors. For its part, Intel discussed its take on multiple-gate transistors at its Intel Developer Forum this fall. The chip powerhouse looks likely this time to concentrate on discussing its forthcoming 90-nanometer manufacturing process, which pairs strained silicon and other new materials to boost performance. It will present separate papers on the process for PC chips and for communications processors. But beyond that, the company is particularly proud of its ability to implement strained silicon for a low cost. The technology is a "key part of our strategy now and one of the elements that we use to extract more performance out of our transistors," said Mark Bohr, an Intel research fellow specializing in manufacturing technology. "It's going to go into manufacturing next year and in a cost-effective manner. That's a significant accomplishment." The use of strained silicon raises chip manufacturing costs by 1 or 2 percent for a performance gain of 10 percent to 20 percent, Bohr said. IBM looks likely to bring strained silicon to market later than Intel. Initially, the company said it would introduce strained silicon in 2003. However, it has since decided it can reach the performance levels it needs at the next process step -- the 90-nanometer level -- using existing technologies such as silicon on insulator. IBM now plans to introduce strained silicon in its 65-nanometer manufacturing technology, which lies two chip generations and about three years in the future, said Jeff Welser, a project manager at IBM Microelectronics. News.com's Michael Kanellos contributed to this report.
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