Intel sees Moore's Law wall ahead

Manufacturers, however, have had to delay the introduction of new processes recently. Using a three-year calendar, 5-nanometre chips won't hit until 2018 or 2019, putting a barrier generation at about 2021. The ITRS timetable will provide more details about the different manufacturing technologies for a given year.

The tunnelling effects, Gargini said, will occur regardless of the chemistry of the transistor materials. Several researchers over the years have predicted the end of Moore's Law but made the mistake of extrapolating on the basis of existing materials.

Designers, however, continually change the materials and structures inside semiconductors. Intel and rival Advanced Micro Devices, for instance, are looking at replacing silicon transistor gates with metallic gates so that chips can be mass-produced with 45-nanometre manufacturing -- expected between 2007 and 2009. Gates on this process will be about 18 nanometres, according to the ITRS timetable.

The concept behind the Intel researchers' paper was, "why don't we do something based entirely on fundamental principles?" Gargini said. "The beauty of our paper is that it is independent of materials."

Theoretically, chip designers could squeeze the size a bit more. "You could probably go to four [nanometres]," he said, but that would require increasing the energy needed to run the chip to make the barrier less susceptible to tunnelling.

Energy a burning problem
Energy consumption, however, is already a major problem for chip designers. Not only is it increasingly difficult to provide energy to a chip, the ambient power-driven heat can cause major malfunctions.

"Scaling for binary switches, packed to maximum density, is ultimately limited by the system capability to remove heat," the paper stated. "Simultaneous gains in packing density and speed of operation will eventually be replaced by a trade-off between packing density and speed in order to satisfy heat removal constraints."

Like other researchers, Gargini sees no easy solution to energy consumption. Active cooling systems can reduce the internal temperature of computers but require independent energy sources, which create about as much heat as they remove. As a result, even if transistors with gate lengths that measure three nanometres could be made, a chip that contained them would hypothetically overheat itself.

"From a total energy point of view, you are not fooling mother nature," Gargini said.

Even if the energy consumption and tunneling problems can be solved, transistors will hit a limit when the gate reaches 1.5 nanometres in length, he said. The number comes from a calculation researchers made when examining what is the smallest well from which an electron could be extracted, Gargini said.

Unlike a conventional transistor, where the source, channel and drain sit in a horizontal line, a transistor at the 1.5-nanometre level might be vertically structured. On the shrinkage rules, transistors with this sort of gate would occur about four to six years after the transistors with 5-nanometre gates, or 2017 to 2025.

One extremely theoretical potential idea is to reuse electrons. In current architectures, electrons travel from a source to a drain and then are destroyed. With recycling, "you simply transfer the electron to something else," Gargini said. "You can make a lot of calculations without destroying the electrons."

Carbon nanotubes and silicon nanowires are another alternative. Transistors made of these materials are of comparable sizes. Carbon nanotubes have a diameter of one to two nanometres, but they are stretched lengthwise between a source and drain in experimental transistors. In the end, performance could go up -- and energy consumption could decline -- but size will stay about the same.

"Exotic structures, such as carbon nanotubes, may find their way into CMOS (Complementary Metal Oxide Semiconductor) applications, not so much driven by acceleration of the scaling cadence, but more likely to enhance the performance of CMOS devices, or perhaps to simplify fabrication," the paper stated. "Even if entirely different electron transport devices are invented for digital logic, their scaling for density and performance may not go much beyond the ultimate limits obtainable with CMOS technology, due primarily to limits on heat removal capacity."

Another alternative is to make the chips bigger, add transistors by adding more real estate or building 3D chips, in which layers of transistors form a high rise. These solutions have been conjectured by Intel co-founder Gordon Moore and Stanford professor Tom Lee, among others.