Sun proposes wireless revolution

A new technology being researched in Sun's labs, called proximity communication, bypasses the wires that connect chips in current designs in favour of a direct connection between chips. "We could maybe see something in 2008 or 2009," Marc Tremblay, chief architect of Sun's scalable systems group, said at a meeting on Monday with reporters.

Sun is developing the proximity communication technology in conjunction with a supercomputing programme funded by the Defense Advanced Research Projects Agency. Sun is competing with IBM and Cray to create a new high-end computing design by 2010 in that program, but Sun hopes to use proximity communication in mainstream computers as well.

Tremblay highlighted the technology, along with features of coming processors code-named Niagara and Rock, on the eve of Intel Developer Forum, a show here where Sun rival Intel boasts of its own technology improvements.

Sun has had troubles with its chip designs in the past, with long delays on the UltraSparc III design and the cancellation of the UltraSparc V processor. But things are looking up now, in particular with Niagara-based systems due in 2006, said Microprocessor Forum Editor Kevin Krewell.

"They're on the road to recovery, that's for sure," Krewell said. And the proximity interconnect idea is promising if Sun can overcome manufacturing challenges such as precise chip alignment. "Eliminating wires can result in significant improvements in performance."

Niagara systems are due in early 2006; a sequel called Niagara 2 should show up in 2007 or 2008 and bring improved networking and Java software performance to the line, Tremblay said. Rock systems are due in 2008.

Catching up with Moore's Law
Communication with today's chips is a complicated process. The chips are fitted with pins that plug into sockets that connect to wires that lead to other chips' sockets. One problem with the approach: Communication speeds within the chip have improved much more quickly than communication speeds between chips.

Proximity communication, which is working in Sun labs, uses a technology called capacitive coupling. In it the electrical state of a tiny patch of one chip is registered by a corresponding patch on another chip that's separated by a thin air gap.

The technology not only is much faster than regular wires, but its performance doesn't lag as the chips speed up, Tremblay said. Essentially, that means chip communications can participate in the same steady Moore's Law pace of processor improvements.

Proximity communication is most likely to be used first to connect proprietary chips -- for example, two central processors or one central processor with a memory controller chip, Tremblay said.

Even though a major bottleneck in computer design today is the comparatively slow connection between processors and memory, proximity communication isn't initially likely to be used for memory. That's because doing so would mean a computer maker no longer could tap into the mass market for standard and comparatively inexpensive memory, Tremblay said.

Proximity communication is likely to be used outside of Sun as well. "It's not a panacea, but it certainly helps. I think you'll hear more about it real soon," Krewell said.

Disintegrating chips
One consequence of proximity communication could be smaller chips, Tremblay said.

Current trends have led designers to integrate more functions onto a single slice of silicon as new manufacturing processes permitted the addition of more circuitry. But physically larger chips come with a penalty: The more silicon real estate is needed, the greater the chances a manufacturing defect will spoil the whole thing.

For example, a silicon chip -- called a die -- that measures 400mm² has four times the surface area of a die measuring 100mm², but higher defect rates mean it costs roughly 16 times as much to manufacture, Tremblay said.

Because proximity communication is nearly as fast as communication within the chip, though, it means separate functions could be split onto separate chips instead of integrated, Tremblay said.

"It would be nice if you could partition a 400mm² die into four 100mm² dies," Tremblay said.

The result probably won't be a reversal of the current trend towards multicore chips, he said. But it might well slow down the growth in die size, he said.