Paulo Gargini is the director of technology strategy at Intel. He describes what he does as long-range research. "I'm very happy when after ten or 15 years I see an idea come into production," he explains. He hosted a question and answer session at the Spring 2006 Intel Developer Forum.
Q: How far are you along in 45nm chip design? Have all the decisions been made.
A: Just to give you an idea, if you stay on the two-year cycle between process revisions you need to have the technology say 80-85 percent defined by now if you want it in 2007. So by the middle of this year we should have made all the decisions. The 65nm process went into manufacture in the fourth quarter of 2005, which means we want 45nm in the fourth quarter of 2007. At the end of 2006 all the equipment has to be in place. So by the end of this year, all decisions will be made. We're 80 percent there.
Are you going to continue to be able to use dry lithography on future processes? [IBM has recently announced it is using immersion lithography, where chips are immersed in a fluid that bends laser light to get smaller feature sizes.]
We work in probabilities, we're large enough to have dry, wet and DUV [Deep Ultraviolet]. We have prototypes of all three. Can we go all the way to 32nm with dry, or do we need immersion? We don't know. We have until the end of 2007 to make the hard decision. We haven't closed the door to EUV [Extreme Ultraviolet]. This year for the first time two of the EUV machines will be delivered to researchers in other organisations, and they will be capable of making ten wafers an hour. If they work and the manufacturer can deliver and they're cost effective then we'll take them. The majority of 32nm work will be DUV, with some EUV. The 22nm process certainly can't use DUV.
How far are MEMS [Micro Electro Mechanical Systems] away from production?
MEMS are very interesting, making things like sensors that we couldn't have made in the past. One problem is that the volume is very low. The most successful market is the automobile. That's a market of 60 million units a year, split among 15 players and divided by the number of models — that's not worth it. So it will take more time than people expect. There are some interesting possibilities in wireless, making the array of an antenna adjustable by nanotechnology, for example. In five years, it'll be much more interesting.
What's happening with carbon?
From 2001 to 2002, 70 percent of carbon nanotubes we produced in the labs were semiconducting. That's now 90 percent. We're on track between 2012 and 2015 to have carbon nanotube semiconductors in production. It won't be mainstream, but we are on track.
Are there heat problems with stacking chips together?
With stacking you have to make sure that the power dissipation is controlled. You can stack anywhere from five to eight or ten packages without too much of a problem. Most mobiles use a microcontroller with NVRAM and RAM stacked, for example. The one on top is very thin, making it very easy to take heat out of the top. We're learning to take it out of the bottom. We'll start with two, learn how to do that, and move on.
What will happen when you reach the limits of silicon?
For the past 30 plus years, we've been applying scaling to silicon. Silicon has two advantages: it is very stable so a wafer 1mm thick won't buckle; and on the surface you can electrically grow silicon dioxide — an insulator that lets you create separate components. That silicon dioxide layer is 1.2nm thick in manufacturing, which means there are just four to five atoms that separate the polysilicon gate from the silicon well. We can't scale past three, two, one, none. And as you scale transistors, the mobility decreases — mobility is a measure of how easy it is for an electron to move from one part of a crystal lattice to another. Capacitance times mobility sets performance. We've been concentrating on capacitance, because it comes for free with scaling. Now we've got to look at mobility.
Strained silicon accelerates mobility by up to a factor of two, but then you reach the limits of silicon. So what else has a high mobility? There are at least six or seven semiconductors with higher mobility. How do you make them? You can't make wafers like you can at the moment. What we can do is selectively deposit other materials on the silicon. So you can't make a [element groups] III/V wafer, but you can deposit the materials on the wafer. Replace islands of silicon with islands of other semiconductors, and you're in a whole new world. Expect it in the second half of next decade.
