Less volts, more power

Server designers are in two minds about power. The power they talk about in adverts is good -- more bits at more gigahertz equals more server performance. Unfortunately, the laws of physics say this sort of power is achieved at the expense of another -- old-fashioned electrical watts. The faster a processor goes and the more information it shifts around, the more power it consumes.

As server farmers rarely worry about the electricity consumption of equipment -- unless operating in a place with intermittent or no mains supply -- the biggest problem of ever-increasing power consumption is heat. A 3.2GHz Xeon is rated at 92 watts dissipation, which means an eight-way Xeon server will be producing more than three-quarters of a kilowatt in waste heat. This is a challenge even in a system with ample space for air movement, powerful fans and active cooling: in high component density server configurations such as blade servers, it can become unfeasible. The complementary side to this is that low power server chips can be packed more densely into a given space and more of them can run simultaneously on a given power supply.

Heat is generated in processors through two main mechanisms, switching and leakage. Every time voltages change across a chip, current has to flow into and out of components -- and this current heats up the parts of the chip through which it moves. On nearly all processors, these voltage changes happen each time the clock switches -- so faster clocks mean more power dissipated. Leakage is less significant but it's still important: as the size of components on a chip reduce, the isolation between their electrodes also reduces and more electricity can leak through.

There are many approaches to reducing power consumption, such as reducing the clock speed, reducing the number of internal operations per instruction, reducing the number of switches per operation and designing the transistors on the chip so that they need less energy each time they switch. Smart control of internal cache is also useful, where only the area in use at any one time is active, and this can be extended to other on-chip areas; if you're primarily operating on data pointers in memory, there's no sense in having the floating-point unit running.

Also, designing the instruction set of the chip so that it can execute software more efficiently with a minimum of data transfers and unnecessary operations can be effective -- this approach has been taken by Intel, whose Pentium processors translate the instructions they get into internal micro-operations, and most spectacularly by Transmeta with its Crusoe and Efficeon chips.

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