Inside Intel's Napa platform

Intel's new Centrino Duo mobile platform (previously codenamed Napa) comprises the Core Duo (Yonah) processor, the PRO/Wireless 3945ABG wireless networking module and the 945 Express chipset.

Yonah's two cores are functionally identical mirror images of each other, which simplifies the routing of common signals between them. Apart from duality, Yonah's biggest -- or smallest -- change is its architectural feature size, shrunk to 65nm from its predecessor Dothan's 90nm. This smaller size keeps the processor line in track with the precepts of Moore’s Law, and gives the designers more room to trade off performance against power consumption. Intel claims that Yonah has twice and Merom will have three times the integer performance per watt of Banias, the 130nm mobile chip that kicked off this line of designs.

Napa and Sonoma platforms compared
Platform	Sonoma (2005)	Napa (2006)
CPU	Dothan (single core, 90nm)	Yonah (dual core, 65nm)
Frontside bus (FSB)	533MHz	667MHz
Wireless	2915ABG (Mini-PCI)	3945ABG (MiniCard)
Memory	DDR2 (400/533MHz)	DDR2 (533/667MHz)
Chipset	915 & ICH6-M	945 & ICH7-M
ODD	Parallel ATA	Serial ATA
Graphics	GMA900	GMA950
Ethernet	Integrated 10/100 (based on PCIe)	Integrated 10/100/1000 (based on PCIe)
Audio	Intel High Definition Audio	Intel High Definition Audio

Lower power consumption
Power consumption has been a big issue in Yonah's creation. A lot of attention has been paid to the leakage current -- the power taken when the chip isn’t doing any processing at all. Although this is typically a few billionths of a watt per transistor, with 151 million transistors it becomes a major issue. Various techniques can improve the situation, such as switching off power altogether to idle areas of the chip and changing the transistor geometry and composition to improve the insulation between its components. Intel says that it's now designing for power consumption in the same way that it has always designed for minimal chip area and most effective timing, but that deciding to do this came about almost by accident: it found big power advantages while designing for aggressive area reduction just as the market started to worry about watts.

The cores themselves have a complex series of power saving options: Active, Halt, Clock Stopped, Sleep, Deeper Sleep and Enhanced Deeper Sleep, which successively push the chip deeper into a coma from which it takes successively longer to return. Each core can slip into the appropriate mode independently of the other; dynamic power management also watches the frequency and power trade-offs for portions of the cores. The cores can finesse their frequencies as appropriate, but don’t have independent voltage control; Intel says it looked at this, but that the form factors for multiple off-chip voltage regulators and the complications caused by routing split high-quality power feeds across the circuit board made this an unappetising option.

Off-chip factors haven’t been ignored. More precise thermal monitoring of hotspots on the chip should mean that power isn’t wasted spinning the cooling fan before it's needed. The chipset can also be safely powered down when the CPU is asleep through a process rather cutely called Dynamic Bus Parking. The chipset itself can abandon main memory to self-refresh mode during enhanced deeper sleep; it can minimise the amount of memory accessed by the display, dim the backlight automatically and compensate by lightening the LCD’s pixels, and read an external sensor to reduce the brightness when the computer is being used in low light levels.

Cleverer cache
Back in the CPU, the Level 2 cache is a major part of Yonah’s design. The 2MB of L2 cache is dynamically allocated between the two cores -- the busier core gets more cache. If one core is idle, the whole of the L2 cache becomes available to the other; if both cores are idle, then the cache can go into one of a number of sleep modes, including one where some or all of the data is written out to main memory and some or all of the cache is physically turned off. Improvements to the caching algorithms and deeper write buffers also reduce expensive main bus traffic, which would otherwise reduce performance and increase power consumption.

Both cores share a single bus into the cache, and data that's shared between processes on different cores can be accessed by either core without creating main bus traffic. This is unlikely to be much of an issue in typical notebook use, but is an example of an architectural feature that may become more important as the chip design filters into servers. It also compensates somewhat for the lack of a dedicated interprocessor bus.