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FPGA Design of Boyer-Moore Algorithm for Spyware Detection
White Papers Hence, the paper proposed the implementation of a hardware implementation of spyware detection using configurable hardware called Field Programmable Gate Array (FPGA). The FPGA apply Boyer-Moore algorithm which is a pattern matching algorithm in...
[October 14, 2008, 1:01]
Rapid Context Switching on an FPGA Custom Processor With a Configurable Number of Registers
White Papers Both the xr16 and xr16rsc have been implemented on a Field Programmable Gate Array (FPGA) chip. The number of application tasks is determined at compilation time and the resulting source code for programming the FPGA chip is produced automatically.
[November 25, 2008, 23:00]
A Novel Low-Power FPGA Routing Switch
White Papers This paper proposes a new programmable FPGA routing switch that can operate in three different modes: high-speed, low-power or sleep. The applicability of the new switch is motivated through an analysis of timing slack in industrial FPGA designs.
[July 11, 2008, 1:02]
A Practical FPGA-Based Framework for Novel CMP Research
White Papers An alternative to simulation is to exploit the rich capabilities of modern FPGAs to create FPGA-based platforms for novel CMP research. Chip-MultiProcessors (CMPs) are quickly gaining momentum in all segments of computing.
[April 18, 2007, 1:00]
RAMP-White: An FPGA-Based Coherent Shared Memory Parallel Computer Emulator
White Papers RAMP-White is an FPGA-based coherent shared memory research platform. It is one of the three initial prototypes being developed by the RAMP (Research Accelerator for Multiple Processors) group. In the spirit of the RAMP project, RAMP-White has been...
[May 26, 2007, 1:00]
On the Design of an FPGA-Based OFDM Modulator for IEEE 802.16-2004
White Papers The work discussed in this paper presents the design, validation and FPGA based implementation of an "Orthogonal Frequency Division Multiplexing" (OFDM) modulator for IEEE 802.16 using a high level design tool, and also reports the resources...
[January 8, 2008, 2:44]
An FPGA-Based Network Processor for IP Packet Compression
White Papers In the demonstration application, FPGA technology is used in conjunction with traditional RISC micro-processors to perform IP packet compression in hard-ware, using a CAM-based hardware implementation of the Lempel-Ziv (LZ) compression algorithm.
[December 27, 2007, 0:01]
Implementation of High Speed Streaming Video Data Transfer Application on FPGA
White Papers The design is implemented on low power FPGA device. This paper highlights a FPGA based SoC architecture for a high resolution streaming video capture device which takes care of low power and high speed design issues.
[October 22, 2008, 1:01]
A Network on Chip Based Gigabit Ethernet Router Implemented on an FPGA
White Papers This paper shares the experiences gained from implementing an FPGA-based gigabit Ethernet router based on the SoCBUS network on chip architecture. Another reason is to evaluate how SoCBUS performs in an FPGA.
[July 4, 2008, 1:00]
Binary LNS-Based Naive Bayes Inference Engine for Spam Control: Noise Analysis and FPGA Implementation
White Papers The inference engine design is synthesized targeting the Altera Stratix FPGA device. A hardware architecture for naive Bayes inference engine in the context of e-mail content classification for spam control is proposed.
[November 28, 2008, 23:00]
Compiling PCRE to FPGA for Accelerating SNORT IDS
White Papers Deep Payload Inspection systems like SNORT and BRO utilize regular expression for their rules due to their high expressibility and compactness. The SNORT IDS system uses the PCRE Engine for regular expression matching on the payload.
[May 21, 2008, 1:01]
The Netezza FAST Engines Framework: A Powerful Framework for High-Performance Analytics
White Papers The Netezza Performance Server (NPS) performance multiplier effect is the result of a framework of FPGA-Accelerated Streaming Technology (FAST) Engines that leverage the embedded FPGA to provide performance acceleration advantages and...
[March 12, 2008, 0:01]
FIR HDL Writer
Downloads FIR HDL Writer is an EDA tool which generates FIR filters in clear text Verilog which may be synthesized to FPGA's or ASIC's. Since verification has become a greater part of the work load for FPGA and ASIC developers, the FIR HDL Writer...
[May 30, 2007, 8:00]
Stay open to new thinking
Leader It's a good bet your company doesn't have an FPGA strategy. But up in Scotland, co-operation between SMEs and academia at the Edinburgh Parallel Computing Centre (EPCC) has produced an FPGA supercomputer showing the sort of figures that Intel or...
[March 22, 2007, 16:25]
Java Debug Hardware Models Using JBits
White Papers This paper presents a methodology for extending FPGA bitstream-level debug and simulation capabilities, through the inclusion of Java/JBits-based hardware device models. Java lends the advantages typically associated with object-oriented design...
[February 1, 2009, 0:00]
A Flexible Solution for Industrial Ethernet
White Papers This white paper describes the use of FPGA devices to deliver a multi-standard Industrial Ethernet capability from a single printed circuit board implementation. The benefits of FPGA implementation are described and an overview of the FPGA...
[July 4, 2008, 1:00]
Syntax-Driven Implementation of Software Programming Language Control Constructs and Expressions on FPGAs
White Papers This paper considers the efficient parallel implementation of control constructs and expressions written in a common software programming language and synthesised to FPGA platforms. Each statement and expression rule in the grammar is implemented...
[January 1, 2009, 23:00]
Stalking Horse by the Biggest Patent Troll on the Planet
Blog Perhaps Microsoft is using this patent to push against Android OS being used on FPGA based CPU's. Most of the products a FPGA could be easily used in would be net books or upscale handheld PDAs or smart phones.
[December 30, 2008, 8:31]
Automatic Compilation Framework for Bloom Filter Based Intrusion Detection
White Papers This paper describes an FPGA-based implementation of the Bloom filter virus detection code that is compiled from the native C to VHDL and mapped onto a Virtex XC2V8000 FPGA. The results show that a single engine tailored for handling virus...
[May 21, 2008, 1:01]
Green supercomputer unveiled in Edinburgh
News Called Maxwell, the computer has been built at the University of Edinburgh and uses field programmable gate arrays (FPGA) in place of conventional microprocessors. FPGA chips differ from standard microprocessors as the silicon can be rewired for...
[March 21, 2007, 9:22]
