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Super CSP: The Wafer Level Package
White Papers The wafer with bump is encasulated in one batch by using a new transfer molding encapsulation method. This technology, which has just been demonstrated conceptually in prototype levels, encompasses 3 major areas: 1)
[August 14, 2003, 0:00]
High-Sensitivity, High-Speed, Dark-Field Wafer-Inspection System
White Papers This paper describes a new dark-field wafer inspection system for detecting particles and defects in patterned wafers. In regard to semiconductor fabrication processes, the use of copper interconnection, high-or low-dielectric-constant materials...
[December 24, 2004, 2:00]
Low-Cost Wafer Bumping
White Papers As the demand for flip-chip interconnects mounts across an increasingly large spectrum of products and technologies, several wafer-bumping processes have been developed to produce the small solder features required for this interconnects technology.
[March 9, 2007, 0:00]
Semiconductor Wafer Foundry Partners With EMC
White Papers In its quest for quality excellence, 1st Silicon (Malaysia) Sdn. Bhd. Si) has formed many strategic supply-chain partnerships, including one with Integrated Circuit Design Service (ICDS). Due to its business growth, ICDS was compelled to look for...
[March 1, 2007, 0:00]
World's First Working 32nm Device At IDF, Nehalem Design Finished.
Blog Paul Otellini just showed off "the world's first working 32nm device" - a wafer containing test memory circuits, 291 megabit RAM chips with 1.9 billion transistor per die. The design is complete - it was finished a month ago (here, Otellini holds...
[September 18, 2007, 17:05]
Process Characterization Of An Ultra-Thick Strippable Photoresist Using A Broadband Stepper
White Papers Lithographic applications that require photoresist with coating thicknesses of greater than 50mm are rapidly growing in the areas of micromachining and wafer level packaging. The semiconductor manufacturing industry is rapidly converting to wafer...
[April 30, 2004, 1:03]
Chip Gear Manufacturers Look Forward To Bumper Year
News Last year, sales of wafer fabrication, packaging and assembly, and testing equipment totaled $22.8 billion. We expect a continuation of strong demand in the back-end segment and finally a strong revival for wafer fab equipment this year," Klaus...
[April 9, 2004, 20:45]
Swinging Nanotubes Point Way To Next-generation RAM
News Using carbon nanotubes a billionth of a metre in diameter sprinkled onto a silicon wafer, the device has been made using mostly standard chip production techniques. The company said that it solved the alignment problem by processing the wafer after...
[June 13, 2003, 14:37]
IBM Combination Technique Speeds PC Chips
News The company has managed to combine both strained silicon and a silicon insulator into the same wafer. The concept -- which involves embedding a layer of silicon and large germanium atoms deep into the wafer to spread out pure silicon layers above...
[September 9, 2003, 16:55]
Rupert Goodwins' Diary
Blog But if you have hundreds of chips on that same wafer of silicon, they cost a hundredth as much for almost exactly the same production cost. So, trick one is to make the individual circuits smaller -- that way you get more per wafer.
[April 8, 2001, 22:20]
IBM Talks Up Power-saving Chips
News Under its new process, IBM said it will be able to build Silicon Germanium bipolar chips on a special type of thin wafer, known as silicon on insulator (SOI). The technique should allow chip designers to mix many more types of circuits on a single...
[September 30, 2003, 8:35]
UMC Produces First 45nm SRAM
News Immersion lithography is used to enhance resolution by putting a liquid medium between the scanner optics and the wafer surface, instead of an air gap. The result is more accurate patterns imprinted on the silicon wafer, the company said.
[November 20, 2006, 23:00]
Intel's McKinley Is One Big Chip
News Intel now carves about 180 of the latest Pentium 4s from a single wafer. Big chips cost more to make because fewer can be carved out of a single wafer. Yields -- the number of good chips produced from a wafer -- also typically declines as chip size...
[February 4, 2002, 8:48]
Nanowires!
Blog First, take your silicon wafer. Take your wafer covered in tiny gold particles, heat it up until the gold melts and stick it in an atmosphere of a gas containing more silicon. The vaporous silicon dissolves in the gold dots until no more can be...
[June 24, 2008, 12:41]
Hybrid Integration Of Light Emitters And Detectors With SOI Based Micro-Opto-Electro-Mechanical Systems (MOEMS)
White Papers The approach taken by the consortium to overcome this issue is to use the single-crystal-silicon (SCS) device layer of a Silicon-on-Insulator (SOI) wafer for the primary structural layer. Flip-chip bonding techniques are also being developed for...
[February 6, 2004, 2:44]
IBM, AMD Team Up To Strain Silicon
News According to early data, DSL improves transistor performance in its chips by 24 percent, but incorporating it does not decrease the number of good chips that come out of a wafer, meaning that it should be relatively inexpensive to adopt.
[December 13, 2004, 8:15]
Molecules Draw Straight Line
News Currently, creating circuits on silicon chips involves several hundred different procedures, including coating the wafers with metallic vapours, printing circuit patterns that have been shrunk to microscopic dimensions onto wafer surfaces, and...
[July 24, 2003, 7:54]
Itanium 2 Shrinks To Fit
News Large chips cost more to make because fewer can be carved out of a single wafer. Yields -- the number of good chips produced from a wafer -- also typically decline as chip size increases because of a greater potential for defects, according to...
[June 12, 2002, 14:03]
Intel To Postpone Chip Factory In Ireland
News Delaying the plant will also let the company more aggressively gear up for 300mm wafer production in 2002. A single 300mm wafer can produce roughly 225 percent more wafers, which leads to lower overall costs.
[December 13, 2000, 12:16]
Tiny Chip As Hot As Venus
News Semiconductor designers, for instance, currently layer chemicals onto wafers by heating a wafer in a chamber to several hundred degrees Celsius, dispersing a metallic vapour, and then cooling the chamber to let the metal adhere.
[July 5, 2004, 14:35]
